Memories in digital computers generally include a plurality of dynamic random access memory (DRAM) chips. Conventional DRAMS are generally arranged in a square array. For example, a conventional 256K. DRAM has 512 rows and 512 columns, and a conventional 1 megabit DRAM has 1,024 rows and 1,024 columns.
DRAMS have row select lines and column select lines. A DRAM is operated by first selecting a row and next selecting a column. The amount of time required to select a column is considerably less than the amount of time required to select a row. It is possible to execute a relatively slow row select operation and to then quickly select a number of columns from that row. The type of operation wherein a slow row select is followed by several fast column selects is generally referred to as a page mode operation of a DRAM. In page mode, one can select words within a page much faster than one can select words which are on different pages.
Another characteristic of conventional DRAMS is that prior to the selection of a row, the row select line must be pre-charged. If one seeks to read sequential locations which are on different rows, after the first read cycle, one must wait for the pre-charge portion of the cycle to be completed before one can execute another read operation. In order to avoid this problem, one can use a known technique termed interleaved memory. In a conventional interleaved memory, there is an "even" memory bank and an "odd" memory bank. Any two sequential memory locations are stored in different memory banks. If one reads two sequential memory locations, the operation is as follows: the first location is read in the first memory bank and while that bank is being pre-charged, the second location is read from the second memory bank. Thus, since two sequential locations will be in different banks, they can be read very quickly without waiting for an intervening pre-charge cycle.
The interleaved memory technique is based on the premise that there is a reasonably high probability that sequential accesses to memory will be in successive memory locations. Thus, sequential memory locations are placed in different banks so that they can be accessed quickly.